The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus of the type in which information is transmitted among a plurality of information handling units such as a central processing unit (hereinafter referred to as a CPU), memories, input-output units and the like through a common signal transmission path (hereinafter referred to as a bus).
A conventional data processing system such as a microcomputer usually includes a plurality of information handling units such as a CPU, memories, and input-output units and, the individual information handling units are coupled to a single data bus, the data being transmitted to and from the individual units through the single data bus. When information handling units designated by a CPU employ the data bus, the remaining non-designated information handling units must stop their processing. In particular, a CPU must always stop its operation during the time when the data bus is employed by the other units, even if processing to be performed in the CPU at that time requires no use of the data bus. Therefore, waiting time is inevitable in the prior art system with the single data bus, which unnecessarily lengthens the processing time.